// sram.v

// Generated using ACDS version 13.0 156 at 2013.09.02.13:55:44

`timescale 1 ps / 1 ps
module sram (
		input  wire        clk_clk,               //        clk.clk
		input  wire        reset_reset_n,         //      reset.reset_n
		input  wire [19:0] sram0_s_address,       //    sram0_s.address
		input  wire [1:0]  sram0_s_byteenable,    //           .byteenable
		input  wire        sram0_s_read,          //           .read
		input  wire        sram0_s_write,         //           .write
		input  wire [15:0] sram0_s_writedata,     //           .writedata
		output wire [15:0] sram0_s_readdata,      //           .readdata
		output wire        sram0_s_readdatavalid, //           .readdatavalid
		inout  wire [15:0] sram0_wire_DQ,         // sram0_wire.DQ
		output wire [19:0] sram0_wire_ADDR,       //           .ADDR
		output wire        sram0_wire_LB_N,       //           .LB_N
		output wire        sram0_wire_UB_N,       //           .UB_N
		output wire        sram0_wire_CE_N,       //           .CE_N
		output wire        sram0_wire_OE_N,       //           .OE_N
		output wire        sram0_wire_WE_N,       //           .WE_N
		inout  wire [15:0] sram1_wire_DQ,         // sram1_wire.DQ
		output wire [19:0] sram1_wire_ADDR,       //           .ADDR
		output wire        sram1_wire_LB_N,       //           .LB_N
		output wire        sram1_wire_UB_N,       //           .UB_N
		output wire        sram1_wire_CE_N,       //           .CE_N
		output wire        sram1_wire_OE_N,       //           .OE_N
		output wire        sram1_wire_WE_N,       //           .WE_N
		input  wire [19:0] sram1_s_address,       //    sram1_s.address
		input  wire [1:0]  sram1_s_byteenable,    //           .byteenable
		input  wire        sram1_s_read,          //           .read
		input  wire        sram1_s_write,         //           .write
		input  wire [15:0] sram1_s_writedata,     //           .writedata
		output wire [15:0] sram1_s_readdata,      //           .readdata
		output wire        sram1_s_readdatavalid  //           .readdatavalid
	);

	wire    rst_controller_reset_out_reset; // rst_controller:reset_out -> [sram_0:reset, sram_1:reset]

	sram_sram_0 sram_0 (
		.clk           (clk_clk),                        //        clock_reset.clk
		.reset         (rst_controller_reset_out_reset), //  clock_reset_reset.reset
		.SRAM_DQ       (sram0_wire_DQ),                  // external_interface.export
		.SRAM_ADDR     (sram0_wire_ADDR),                //                   .export
		.SRAM_LB_N     (sram0_wire_LB_N),                //                   .export
		.SRAM_UB_N     (sram0_wire_UB_N),                //                   .export
		.SRAM_CE_N     (sram0_wire_CE_N),                //                   .export
		.SRAM_OE_N     (sram0_wire_OE_N),                //                   .export
		.SRAM_WE_N     (sram0_wire_WE_N),                //                   .export
		.address       (sram0_s_address),                //  avalon_sram_slave.address
		.byteenable    (sram0_s_byteenable),             //                   .byteenable
		.read          (sram0_s_read),                   //                   .read
		.write         (sram0_s_write),                  //                   .write
		.writedata     (sram0_s_writedata),              //                   .writedata
		.readdata      (sram0_s_readdata),               //                   .readdata
		.readdatavalid (sram0_s_readdatavalid)           //                   .readdatavalid
	);

	sram_sram_0 sram_1 (
		.clk           (clk_clk),                        //        clock_reset.clk
		.reset         (rst_controller_reset_out_reset), //  clock_reset_reset.reset
		.SRAM_DQ       (sram1_wire_DQ),                  // external_interface.export
		.SRAM_ADDR     (sram1_wire_ADDR),                //                   .export
		.SRAM_LB_N     (sram1_wire_LB_N),                //                   .export
		.SRAM_UB_N     (sram1_wire_UB_N),                //                   .export
		.SRAM_CE_N     (sram1_wire_CE_N),                //                   .export
		.SRAM_OE_N     (sram1_wire_OE_N),                //                   .export
		.SRAM_WE_N     (sram1_wire_WE_N),                //                   .export
		.address       (sram1_s_address),                //  avalon_sram_slave.address
		.byteenable    (sram1_s_byteenable),             //                   .byteenable
		.read          (sram1_s_read),                   //                   .read
		.write         (sram1_s_write),                  //                   .write
		.writedata     (sram1_s_writedata),              //                   .writedata
		.readdata      (sram1_s_readdata),               //                   .readdata
		.readdatavalid (sram1_s_readdatavalid)           //                   .readdatavalid
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS        (1),
		.OUTPUT_RESET_SYNC_EDGES ("deassert"),
		.SYNC_DEPTH              (2)
	) rst_controller (
		.reset_in0  (~reset_reset_n),                 // reset_in0.reset
		.clk        (clk_clk),                        //       clk.clk
		.reset_out  (rst_controller_reset_out_reset), // reset_out.reset
		.reset_in1  (1'b0),                           // (terminated)
		.reset_in2  (1'b0),                           // (terminated)
		.reset_in3  (1'b0),                           // (terminated)
		.reset_in4  (1'b0),                           // (terminated)
		.reset_in5  (1'b0),                           // (terminated)
		.reset_in6  (1'b0),                           // (terminated)
		.reset_in7  (1'b0),                           // (terminated)
		.reset_in8  (1'b0),                           // (terminated)
		.reset_in9  (1'b0),                           // (terminated)
		.reset_in10 (1'b0),                           // (terminated)
		.reset_in11 (1'b0),                           // (terminated)
		.reset_in12 (1'b0),                           // (terminated)
		.reset_in13 (1'b0),                           // (terminated)
		.reset_in14 (1'b0),                           // (terminated)
		.reset_in15 (1'b0)                            // (terminated)
	);

endmodule
